14 March 2022
by Andrea Gaini

Committed to ultra-effective computer memory

Researchers from the Universities of Lancaster and Warwick, UK, have fabricated compound semiconductor ultra-effective memory (ULTRARAM) devices on silicon that they claim would combine the best features of existing memories without any of the disadvantages.

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The approach, they say, would be non-volatile, fast and affordable, offering high endurance and low switching energy.

ULTRARAM uses crystalline compounds made up of elements from group III and group V of the periodic table, namely, aluminium antimonide (AlSb), gallium antimonide (GaSb) and indium arsenide (InAs), which have almost the same lattice constant.

‘The technology is essentially a compound semiconductor version of flash technology used in USB and solid-state drives,’ says Professor Manus Hayne of the University of Lancaster.

‘Both work by storing the data as charge, or a lack of it, in an electrically isolated region called a ‘floating gate’. In flash, the charge is robustly stored, but taking it in and out is difficult, requiring large voltages that make writing and erasing slow, gradually damaging the memory cell.

‘By using the material property design capability available in compound semiconductors, we were able to construct a barrier that switches from insulating to conducting using a voltage that is a fraction of that used in flash.

‘[This barrier] exploits a quantum-mechanical phenomenon, called resonant tunnelling, in which two barriers enclose a resonant cavity, analogous to the cavity in an organ pipe.

‘An electron approaching such a structure will see it as opaque, unless the electron resonates with the cavity, in which case it will pass through. In our devices, to make sure that no electron passes inadvertently, we have three barriers defining two cavities with different resonances. By applying a small voltage across the structure, the cavities can be tuned so that their resonances coincide, allowing electrons to pass through one way or the other, on demand.

‘This triple-barrier resonant tunnelling structure is at the very extremes of materials engineering, with the five layers (three barriers, two cavities) having atomically-precise thicknesses of three, five, two, four and three crystalline lattice spacings, i.e. six, ten, four, eight and six atoms thick (two atom per lattice spacing), which is 1.83, 3.05, 1.22, 2.44 and 1.83nm.’

Hayne notes that there are several materials challenges with implementing this technology on silicon.

‘The first is the change from an elemental semiconductor, i.e. silicon, to III-V compound semiconductors. This is a problem because the first layer of atoms on the silicon surface may be a group III atom in some places, and a group V in other places, which creates defects where those regions join.

‘The second issue is that the crystalline lattice spacing of the silicon is very different from the III-Vs, which creates strain and, again, defects as a result. To solve these problems, we refined and adapted methods previously developed at Lancaster for photonic devices.

‘Finally, the III-Vs and the silicon expand and contract different amounts when you heat them up, which is necessary for the material growth, and cool them back down to room temperature. This one is essentially unsolvable, but tolerable, the end result being that the semiconductor wafer is not completely flat.’

To turn the wafer into useable memory devices, they have used photolithographic processing, said to be more complex here.

Hayne shares, ‘For example, one of the processing challenges is to make direct electrical contact to a 10nm-thick InAs layer below the surface to read out the device. The processing is under constant development and refinement, as is the material design and growth.’

The devices have been tested by applying ±2.5V pulses to programme and erase, while measuring electrical conductivity at room temperature in ambient conditions.

The researchers are working towards 64-bit arrays at 20μm size, scaling single devices to 100nm or below using electron-beam lithography.

‘Thereafter we will need to make much larger arrays of scaled devices. This will be a significant technological challenge, but we are not aware of any fundamental obstacles.’


Andrea Gaini